FIG. 16 shows the configuration of a conventional wireless communication device disclosed in JP-A No. 355198/1999.
As illustrated in FIG. 16, the device includes: a central processing unit CPU (hereinafter called the processor) 1; a frame synchronous circuit SYN (hereinafter called the synchronous circuit) 2; a receiver circuit RCV 3; a register (control means) REG 4; a switching circuit SWC 5; an oscillator OSC 6 which outputs high speed clock CK; a real time clock RTC with a timer function which is used as a clock function of the wireless communication device, RTC (hereinafter called RTC) 7; an input/output circuit I/O (hereinafter called I/O) 8; a timer TIM 9; an interruption circuit INTC 10; and a bus for receiving and transmitting addresses, data and, control data, 11.
The switching circuit SWC 5 selects either clock CK1 outputted from the oscillator OSC 6 or clock CK2 outputted from RTC 7 according to control data from the processor CPU 1 which is written and stored in the register REG 4, and supplies the selected clock to the processor CPU 1, synchronous circuit SYN 2, and register REG 4.
The timer TIM 9 operates all the time according to clock CK2 outputted from RTC 7 and in the intermittent mode (sleep mode) after paging channel reception, time to supply clock CK2 outputted from RTC 7 is set on the timer TM 9 by the processor CPU 1. As the timer TIM 9 times out, it outputs an interruption control signal to the interruption circuit INTC 10 to bring the interruption circuit INTC 10 into an interruption status.
When the interruption circuit INTC 10 receives an interruption control signal from the timer TIM 9 or an interruption request which is keyed in by the user via the I/O 8, it notifies the processor CPU 1 of occurrence of the interruption request. In other words, the interruption circuit INTC 10 outputs the interruption request to the processor CPU 1.
After a timer value is set on the timer TIM 9 by the processor CPU 1, the processor CPU 1 writes control data into the register REG 4. According to the control data stored in the register REG 4, the switching circuit SWC 5 switches clock CK1 outputted from the oscillator OSC 6 to clock CK2 outputted from RTC 7 and sends clock CK2 to the processor CPU 1, synchronous circuit SYN 2, register REG 4 and so on. In this way, the processor CPU 1, synchronous circuit SYN 2, register REG 4, and so on operate in accordance with clock CK2. Furthermore, the oscillator OSC 6 stops operating according to control data written in the register REG 4.
When the processor CPU 1 receives an interruption request from the interruption circuit INTC 10, it decides which circuit has outputted the interruption request. If it decides that the request has come from a circuit other than the timer TIM 9, it processes the request in accordance with clock CK1 and waits for arrival of a next interruption request.
If the processor CPU 1 decides that the received interruption request has come from the timer TIM 9, then it writes control data in the register REG 4. The switching circuit SWC 5 switches clock CK2 from RTC 7 to clock CK1 from the oscillator OSC 6 according to the control data written in the register REG 4. The clock CK1 thus selected is sent to the processor CPU 1, synchronous circuit SYN 2, register REG 4 and so on.